Vol. E90-A, No. 12 December 2007

Published: 2007-12-01

Foreword

FOREWORD

Yusuke MATSUNAGA

2649-2650
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Letters

Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM

Masaaki IIJIMA, Kayoko SETO, Masahiro NUMA, Akira TADA, Takashi IPPOSHI

2691-2694
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Transistor Sizing of LCD Driver Circuit for Technology Migration

Masanori HASHIMOTO, Takahito IJICHI, Shingo TAKAHASHI, Shuji TSUKIYAMA, Isao SHIRAKAWA

2712-2717
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Robust Source Separation with Simple One-Source-Active Detection

Yijing CHU, Heping DING, Xiaojun QIU

2939-2944
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A Class of Cocyclic Quasi Jacket Block Matrix

Moon Ho LEE, Subash Shree POKHREL, Wen Ping MA

2945-2948
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A Digital Image Watermarking Method Using Interval Arithmetic

Teruya MINAMOTO, Mitsuaki YOSHIHARA, Satoshi FUJII

2949-2951
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Fast Parameter Selection Algorithm for Linear Parametric Filters

Akira TANAKA, Masaaki MIYAKOSHI

2952-2956
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Covariance Control for Bilinear Stochastic Systems via Sliding Mode Control Concept

Koan-Yuh CHANG, Tsung-Lin CHENG

2957-2961
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Security Analysis of Zhu-Bao's Verifiably Committed Signature

Dae Hyun YUM, Pil Joong LEE

2962-2964
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A Note on the ε-Overflow Probability of Lossless Codes

Ryo NOMURA, Toshiyasu MATSUSHIMA, Shigeichi HIRASAWA

2965-2970
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An Effective SLM-PRSC Hybrid Scheme for OFDM PAPR Reduction

Seungwoo HAN, Suckchel YANG, Yoan SHIN

2971-2974
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Performance Bound for Finite-Length LDPC Coded Modulation

Huy G. VU, Ha H. NGUYEN, David E. DODDS

2975-2978
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A Hybrid Image Coder Based on SPIHT Algorithm with Embedded Block Coding

Tze-Yun SUNG, Hsi-Chin HSIN

2979-2984
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State Machines as Inductive Types

Kazuhiro OGATA, Kokichi FUTATSUGI

2985-2988
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Papers

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification

Daisuke KOSAKA, Makoto NAGATA, Yoshitaka MURASAKA, Atsushi IWATA

2651-2660
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Timing Analysis Considering Spatial Power/Ground Level Variation

Masanori HASHIMOTO, Junji YAMAGUCHI, Hidetoshi ONODERA

2661-2668
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Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines

Hiroshi KAWAGUCHI, Danardono Dwi ANTONO, Takayasu SAKURAI

2669-2681
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Manufacturability-Aware Design of Standard Cells

Hirokazu MUTA, Hidetoshi ONODERA

2682-2690
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Area Comparison between 6T and 8T SRAM Cells in Dual-V_dd Scheme and DVS Scheme

Yasuhiro MORITA, Hidehiro FUJIWARA, Hiroki NOGUCHI, Yusuke IGUCHI, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO

2695-2702
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An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults

Jin-Fu LI, Chao-Da HUANG

2703-2711
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A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost

Tsung-Yi WU, Jr-Luen TZENG

2718-2726
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Opposite-Phase Clock Tree for Peak Current Reduction

Yow-Tyng NIEH, Shih-Hsu HUANG, Sheng-Yu HSU

2727-2735
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Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements

Bakhtiar Affendi ROSDI, Atsushi TAKAHASHI

2736-2742
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A Relocation Method for Circuit Modifications

Kunihiko YANAGIBASHI, Yasuhiro TAKASHIMA, Yuichi NAKAMURA

2743-2751
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Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs

Shinobu NAGAYAMA, Tsutomu SASAO, Jon T. BUTLER

2752-2761
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BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades

Munehiro MATSUURA, Tsutomu SASAO

2762-2769
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Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders

Taeko MATSUNAGA, Yusuke MATSUNAGA

2770-2777
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Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints

Hiroaki KOZAWA, Kiyoharu HAMAGUCHI, Toshinobu KASHIWABARA

2778-2789
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Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times

Hiroshi SAITO, Naohiro HAMADA, Nattha JINDAPETCH, Tomohiro YONEDA, Chris MYERS, Takashi NANYA

2790-2799
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Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram

Hiroaki TANAKA, Yoshinori TAKEUCHI, Keishi SAKANUSHI, Masaharu IMAI, Hiroki TAGAWA, Yutaka OTA, Nobu MATSUMOTO

2800-2809
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Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs

Kohei HOSOKAWA, Katsunori TANAKA, Yuichi NAKAMURA

2810-2817
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High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC

Chun-Lung HSU, Mean-Hom HO

2818-2825
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An Approach to Solve Local Minimum Problem in Sound Source and Microphone Localization

Kazunori KOBAYASHI, Ken'ichi FURUYA, Yoichi HANEDA, Akitoshi KATAOKA

2826-2834
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A Distortion-Free Learning Algorithm for Feedforward Multi-Channel Blind Source Separation

Akihide HORITA, Kenji NAKAYAMA, Akihiro HIRANO

2835-2845
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An Algorithm to Improve the Performance of M-Channel Time-Interleaved A-D Converters

Koji ASAMI

2846-2852
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Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis

Yuko HARA, Hiroyuki TOMIYAMA, Shinya HONDA, Hiroaki TAKADA, Katsuya ISHII

2853-2862
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`Adaptive Link Adjustment' Applied to the Fixed Charge Transportation Problem

Sang-Moon SOAK

2863-2876
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Kalman-Filter Based Estimation of Electric Load Composition with Non-ideal Transformer Modeling

Soon LEE, Seung-Mook BAEK, Jung-Wook PARK, Young-Hyun MOON

2877-2883
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A Parallel Algorithm for NMNF Problems with a Large Number of Capacity Constraints

Shieh-Shing LIN

2884-2890
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Discrete Program-Size Dependent Software Reliability Assessment: Modeling, Estimation, and Goodness-of-Fit Comparisons

Shinji INOUE, Shigeru YAMADA

2891-2902
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The Vanstone-Zuccherato Schemes Revisited

Naoki KANAYAMA, Shigenori UCHIYAMA

2903-2907
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Improved MACs from Differentially-Uniform Permutations

Kazuhiko MINEMATSU, Toshiyasu MATSUSHIMA

2908-2915
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Group-Linking Method: A Unified Benchmark for Machine Learning with Recurrent Neural Network

Tsungnan LIN, C. Lee GILES

2916-2929
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An Improved Clonal Selection Algorithm and Its Application to Traveling Salesman Problems

Shangce GAO, Zheng TANG, Hongwei DAI, Jianchen ZHANG

2930-2938
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