Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond

Authors

• Noriaki ODA
• Hiroyuki KUNISHIMA
• Takashi KYOUNO
• Kazuhiro TAKEDA
• Tomoaki TANAKA
• Toshiyuki TAKEWAKI
• Masahiro IKEDA